We will create a 256x8  RAM in this example.

VHDL CODE: 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RAM is
     Port ( Clk        : in        STD_LOGIC;           
                Data     : inout   STD_LOGIC_VECTOR (7 downto 0);
                Adress : in        STD_LOGIC_VECTOR  (7 downto 0);
                R_Wn   : in        STD_LOGIC);         
end RAM;

architecture Behavior of RAM is
type RAM_D is array (2**8-1 downto 0)  of std_logic_vector(7 downto 0);
signal RAM_U : RAM_D;
      begin
          process(Clk,R_Wn)
             begin    
                 if (falling_edge(Clk)) then
                       if R_Wn= '1' then--read data from ram 
                              Data<= RAM_U(conv_integer( Adress));
                         else --Write data to Ram 
                                 RAM_U(conv_integer( Adress))<=Data;
                         end if;                           
                  end if;
              end process;
        end Behavior;